The present invention relates to flash memory storage systems and, more particularly, to a flash memory storage system in which multiple bits are stored per flash memory cell and in which certain disturbance effects are minimized.
FIG. 1, which is identical to FIG. 1 of Chen et al., U.S. Pat. No. 6,522,580, is a block diagram of a typical prior art flash memory device. A memory cell array 1 including a plurality of memory cells M arranged in a rectangular array is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5. Column control circuit 2 is connected to bit lines (BL) of memory cell array 1 for reading data stored in the memory cells (M), for determining a state of the memory cells (M) during a program operation, and for controlling voltage levels of the bit lines (BL) to promote the programming or to inhibit the programming. (For historical reasons, writing data to a flash memory is called “programming” the flash memory; the terms “writing” and “programming” are used interchangeably herein.) Row control circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply programming voltages combined with the bit line voltage levels controlled by column control circuit 2, and to apply an erase voltage coupled with a voltage of a p-type region on which the memory cells (M) are formed. C-source control circuit 4 controls a common source line connected to the memory cells (M). C-p-well control circuit 5 controls the c-p-well voltage. Typically, in a NAND flash device, the cells controlled by one word line correspond to one or two pages of the device.
The data stored in the memory cells (M) are read out by column control circuit 2 and are output to external I/0 lines via an I/O line and a data input/output buffer 6. Program data to be stored in the memory cells are input to data input/output buffer 6 via the external I/O lines, and are transferred to the column control circuit 2. The external I/O lines are connected to a controller 20.
Command data for controlling the flash memory device are input to a command interface connected to external control lines that are connected with controller 20. The command data informs the flash memory of what operation is requested. The input command is transferred to a state machine 8 that controls column control circuit 2, row control circuit 3, c-source control circuit 4, c-p-well control circuit 5 and data input/output buffer 6. State machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
Controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from memory array 1, and provides or receives such data, respectively. Controller 20 converts such commands into command signals that can be interpreted and executed by command circuits 7. Controller 20 also typically contains buffer memory for the user data being written to or read from memory array 1. A typical memory system includes one integrated circuit chip 21 that includes controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
Word lines WL are conducting lines that connect the control gates of all cells in a row of cells word line A is illustrated in FIG. 1, the Word lines WL run horizontally from left to right, with the numerical address of the cells along a word line increasing from left to right. Two cells that are adjacent to each other on a word line are said to be “immediate neighbors” along that word line. The word lines within a block of cells are numbered with the numbers increasing from bottom to top, and the programming order of the word lines is assumed to be from low-numbered word lines to high-numbered word lines. Therefore, a given word line is the immediate successor of another word line if its number is larger by one than the number of the other word line. In such a case, the other word line is the immediate predecessor of the first word line. Bit lines BL are conducting lines that connect all cells in a column of cells and are used for inputting and outputting data to/from the cellsbit line. As illustrated in FIG. 1, the Bit lines BL are assumed to run vertically from bottom to top. A first cell is said to be “above” a second cell if both cells are on the same bit line and the first cell is on a word line that is the immediate successor of the word line of the second cell. In such case the second cell is “below” the first cell. Each cell is located at an intersection of a word line and a bit line, and is said to be “on the word line” and “on the bit line”, or alternatively “associated with the word line” and “associated with the bit line”.
U.S. Pat. No. 6,781,877 to Cernea et al., that is included by reference for all purposes as if fully set forth herein, discusses a disturbance in programming flash memory cells that results from capacitive coupling between cells. Flash blocks (a block is the smallest chunk for erasing cells in a single operation) are written in units of pages, where a page is the smallest chunk for writing cells in a single operation from the user point of view (and a block contains multiple pages). Typically, the cells associated with a page share a common word line in the array of flash cells, that word line being connected to the control gates of all those cells. In SLC-type flash memories, each cell stores one bit, and the cells of a page are associated exclusively with that page and with no other page. In MLC-type flash memories, each cell stores multiple bits. In most NAND-type flash devices currently in use the different bits of a cell are associated with different user pages (a “user page” is the chunk of data provided by the user of the flash device in a single programming command, and is herein also called a “logical page”. In contrast, the combination of all user pages stored in the same cells is herein called a “physical page”. A typical user page is currently of a size of 2K bytes, and therefore a corresponding 4-bits-per-cell device has a physical page size of 8 Kbytes. The above sizes ignore some amount of extra cells provided for each page for management purposes, and therefore are only approximations), but there also are MLC devices in which all bits of a multi-bit cell are associated with the same user page. The present invention is applicable to both types of MLC devices. The present invention is also applicable to SLC devices, even though it is most useful for MLC devices that store more than two bits per cell: three bits per cell or four bits per cell or even a higher number of bits per cell. This is because the advantage of the present invention is in increasing the accuracy of programming operations, and such accuracy is most useful when the margin between the threshold voltages of flash cells programmed to different states (to represent different values of stored data) is relatively small, as is the case in MLC devices storing many bits per cell.
In the explanations below we assume that the flash device is of the first MLC type mentioned above. We also assume that a word line corresponds to a single physical page that contains a number of cells that is equal to the number of bits in a logical page. Therefore the word line corresponds to a number of user pages equal to the number of bits per cell in the device. There are flash devices where this is not so and a word line contains multiple (most commonly two) physical pages, each physical page corresponding to multiple user pages. The use of the single-physical-page-per-word line case in the explanations is done only for the sake of simplicity, and the present invention is equally applicable to the multiple-physical-pages-per-word line case.
Flash blocks are typically programmed in sequential order, from the lowest-numbered word line to the highest-numbered word line. Cernea et al. disclose that there is a capacitive coupling between the cells in different word lines, introducing undesired disturbances into the values of threshold voltages attained by the cells. The effect of such coupling is that when programming a cell in word line number N to a relatively high threshold, the threshold voltage of adjacent cells in word line (N−1) are increased. This mainly applies to the cell in word line (N−1) that is directly “below” the currently programmed cell, but is also applicable to a lesser extent to other nearby cells in word line (N−1). See FIG. 2 of Cernea et al. that shows an example of capacitive coupling from a given cell affecting three cells in the word line below the cell.
As the programming of word line N occurs after the programming of word line (N−1), the cells of word line (N−1) remain with a threshold voltage that is higher than intended, possibly causing errors when reading the data. When a block of flash cells is programmed sequentially from first word line to last word line, the capacitive coupling effect introduces errors into cells of successive wordlines—programming the second word line introduces errors into the first word line, programming the third word line introduces errors into the second word line, and so on until programming the last word line introduces errors into the next-to-last word line. The only word line not suffering from the capacitive coupling effect is the last word line, as no other word line of the block is programmed after the last word line.
Even though Cernea et al. discuss only the coupling from a word line to its immediate predecessor word line, the capacitive coupling effect is also known to occur across larger distances between word lines, even though to a much lesser extent. That is the programming of word line N might introduce disturbances into cells of word line (N−2), and even into cells of more distant word lines. The present invention is equally applicable to such longer distance effects, even though for simplicity the explanations are given in terms of the “immediate neighboring word line” case, which is also the most important effect.
It should be noted that it is not possible to use a counter-measure against capacitive coupling of word lines by programming all cells in all word lines (possibly with the exception of cells in the last word line) to threshold voltages that are lower than the desired value by a fixed amount, expecting that when programming the next word line the capacitive effect will increase the threshold voltages and bring the threshold voltages to the desired value. This method cannot work because the effect of the capacitive coupling is not fixed but is dependent on the value programmed into the disturbing cell. A cell programmed to a state of high threshold voltage causes a larger disturbance in its neighbors than a cell programmed to a lower threshold voltage. This data dependency makes it impossible to use a fixed correction to counter the problem.
Cernea et al. propose a solution to the capacitive coupling problem that is based on writing each word line multiple times. A word line is first programmed using somewhat-lower-than-final verify voltages, thus bringing the cells of the word line to lower-than-desired threshold voltages. After the next word line is programmed once, the current word line is programmed again (with the same data) using the final verify voltages, thus making sure all cells end up with their desired threshold voltages. This method creates the following order of operations when filling a block:
a. First programming of first word line.
b. First programming of second word line.
c. Second programming of first word line.
d. First programming of third word line.
e. Second programming of second word line.
The reasoning behind this method is that the final programming of any word line is done when the cells of the next word line are already almost at their final threshold voltages, and so when the cells of the next word line are programmed again, the effect of their capacitive coupling is small. While the first programming of the next word line does affect the threshold voltages of the cells of the current word line after their first programming, the second programming of the current word line (which occurs after the first programming of the next word line) eliminates the effect and narrows the distributions of the cells' threshold voltages around their desired values.
While the method of Cernea et al. seems to solve the capacitive coupling problem in the sense of ending up with the cells being programmed to their desired values with good accuracy, the method has a serious disadvantage. Programming of flash memory is a rather slow operation (compared to reading). Programming almost all word lines twice causes the effective write time of the flash memory device to approximately double, reducing the effective write performance to approximately half. The situation might get even worse when extending Cernea's method to cases where capacitive coupling has to be taken care of not only between adjacent word lines but also between more distant word lines. This is typically the case when the flash cells store more than two bits per cell, as in such cases the accuracy required for reliable programming is high and even relatively small capacitive effects from more distant word lines cannot be neglected. Extending Cernea's method to such cases might require programming cells even more than twice, making the performance problem even more significant.
While the above explanations deal with NAND-type floating-gate flash memory cells, there are other types of flash memory technologies. For example, in the NROM flash memory technology there is no conductive floating gate but an insulating layer trapping the electric charge. The present invention is equally applicable to all flash memory types, even though the explanations are given in the context of floating-gate technology.
Therefore, it is desirable to provide methods for implementing a flash memory device that is more reliable than prior art flash memory devices in the sense of being less vulnerable to capacitive coupling between word lines, while not sacrificing write performance.